Index: src/southbridge/via/vt8237r/romstrap.inc =================================================================== --- src/southbridge/via/vt8237r/romstrap.inc (revision 0) +++ src/southbridge/via/vt8237r/romstrap.inc (revision 0) @@ -0,0 +1,113 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + .section ".romstrap", "a", @progbits + .globl __romstrap_start +__romstrap_start: +tblpointer: +//20 AA 22 50 | C2 0F 97 61 +//20 AA 22 50 | C2 0F 97 61 +//20 AA 22 50 | C2 0F 97 61 +//20 AA 22 50 | C2 0F 97 61 +//20 AA 22 50 | C2 0F 97 61 +//00 00 00 00 | 00 00 00 00 +//dd 0504400AAh, 061970FC2h ;200M +// dd 000000000h, 000000000h +/// dd 0950B6000h, 000F8D0F8h +// dd 0F12C1600h, 000B2CB01h +// +// dd 0504400AAh, 061970FC2h ;400M +// dd 000000000h, 000000000h +// dd 0950B6000h, 000F8D0F8h +// dd 0F12C1600h, 000B2CB01h +// +// dd 0504400AAh, 061970FC2h ;600M +// dd 000000000h, 000000000h +// dd 0950B6000h, 000F8D0F8h +// dd 0F12C1600h, 000B2CB01h +// +// dd 0504400AAh, 061970FC2h ;800M +// dd 000000000h, 000000000h +// dd 0950B6000h, 000F8D0F8h +// dd 0F12C1600h, 000B2CB01h +// +// dd 0504400AAh, 061970FC2h ;1000M +// dd 000000000h, 000000000h +// dd 0950B6000h, 000F8D0F8h +// dd 0F12C1600h, 000B2CB01h + + + .byte 0x20 + .byte 0xaa + .byte 0x22 + .byte 0x50 + .byte 0xc2 + .byte 0x0f + .byte 0x97 + .byte 0x61 + + .byte 0x20 + .byte 0xaa + .byte 0x22 + .byte 0x50 + .byte 0xc2 + .byte 0x0f + .byte 0x97 + .byte 0x61 + + .byte 0x20 + .byte 0xaa + .byte 0x22 + .byte 0x50 + .byte 0xc2 + .byte 0x0f + .byte 0x97 + .byte 0x61 + + .byte 0x20 + .byte 0xaa + .byte 0x22 + .byte 0x50 + .byte 0xc2 + .byte 0x0f + .byte 0x97 + .byte 0x61 + + .byte 0x20 + .byte 0xaa + .byte 0x22 + .byte 0x50 + .byte 0xc2 + .byte 0x0f + .byte 0x97 + .byte 0x61 + + + .long 0x0 + .long 0x0 +this: + .long tblpointer - 0xFFF00000 + .globl __romstrap_end + +__romstrap_end: + + +.previous Index: src/southbridge/via/vt8237r/vt8237r.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r.c (revision 0) +++ src/southbridge/via/vt8237r/vt8237r.c (revision 0) @@ -0,0 +1,100 @@ +#include +#include +#include +#include +#include +#include +//#include +//#include + +#include "vt8237r.h" +#include "chip.h" + +/* Priority: HIGH */ +/* Lots to do in here. Gut out any serial support, since vt8237 doesn't do it. + * Empty or comment out anything magnus doesn't need, I'll do it later */ +/* Low priority: + * Fix hard_reset() + * Finish that stuff I commented out earlier */ + +/* + * Datasheets: http://www.via.com.tw/en/downloads/datasheets/chipsets/ + * VT8237R_SouthBridge_Revision2.06_Lead-Free.zip +*/ + +/* PCI IDs need to be fixed up, I've just replaced all the numbers for now */ +static int enabled = 0; + +// void peg_init(struct device *dev); + +void hard_reset(void) +{ + printk_err("NO HARD RESET ON VT8237R! FIX ME!\n"); +} + + + +void writeback(struct device *dev, int where, int what) { + unsigned char regval; + + pci_write_config8(dev, where, what); + regval = pci_read_config8(dev, where); + if (regval != what) { + print_err("Writeback to "); + print_err_hex8(where); + print_err("failed "); + print_err_hex8(regval); + print_err("\n "); + } + + +} + + +void dump_south(device_t dev0) +{ + int i,j; + + for(i = 0; i < 256; i += 16) { + printk_debug("%02x: ", i); + for(j = 0; j < 16; j++) { + printk_debug("%02x ", pci_read_config8(dev0, i+j)); + } + printk_debug("\n"); + } +} + +void set_led() +{ + // set power led to steady now that lxbios has virtually done its job + //device_t dev; + //dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, 0); + //pci_write_config8(dev, 0x94, 0xb0); +} + + +static void vt8237r_enable(struct device *dev) +{ + struct southbridge_via_vt8237r_config *conf = dev->chip_info; + unsigned char regval; + unsigned short vendor,model; + int i; + device_t dev0; + + vendor = pci_read_config16(dev,0); + model = pci_read_config16(dev,0x2); + + printk_debug("In vt8237r_enable %04x %04x.\n",vendor,model); + + /* FIXME DISABLE USB Device Mode, Internal LAN Controller */ +// regval = pci_read_config8(dev, 0x51); +// regval &= ~0x8; + pci_write_config8(dev, 0x51, 0x8d); + +} + +struct chip_operations southbridge_via_vt8237r_ops = { + CHIP_NAME("VIA VT8237R Southbridge") + .enable_dev = vt8237r_enable, +}; + Index: src/southbridge/via/vt8237r/Config.lb =================================================================== --- src/southbridge/via/vt8237r/Config.lb (revision 0) +++ src/southbridge/via/vt8237r/Config.lb (revision 0) @@ -0,0 +1,7 @@ +config chip.h +driver vt8237r.o +driver vt8237r_ide.o +driver vt8237r_lpc.o +driver vt8237r_nic.o +driver vt8237r_sata.o +driver vt8237_bridge.o Index: src/southbridge/via/vt8237r/vt8237r_ide.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_ide.c (revision 0) +++ src/southbridge/via/vt8237r/vt8237r_ide.c (revision 0) @@ -0,0 +1,122 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Based on other VIA SB code, no native mode. Interrupts from unconnected HDDs + * might occur if IRQ14/15 is used for PCI. Therefore no native mode support. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "vt8237r.h" +#include "chip.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8237r_config *conf = dev->chip_info; + unsigned char enables; + + printk_info("Enabling VIA IDE.\n"); + + enables = pci_read_config8(dev, 0x40); + printk_debug("enables in reg 0x40 0x%x\n", enables); + enables |= 3; //enable both channels + pci_write_config8(dev, 0x40, enables); + enables = pci_read_config8(dev, 0x40); + printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + + + printk_info("%s: enabling compatibility IDE addresses\n", + __FUNCTION__); + enables = pci_read_config8(dev, 0x42); + printk_debug("enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config8(dev, 0x42, enables); + enables = pci_read_config8(dev, 0x42); + printk_debug("enables in reg 0x42 read back as 0x%x\n", + enables); + + + // Enable prefetch buffers + enables = pci_read_config8(dev, 0x41); + enables |= 0xf0; + pci_write_config8(dev, 0x41, enables); + + // Lower thresholds (cause award does it) + enables = pci_read_config8(dev, 0x43); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config8(dev, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config8(dev, 0x44, 0x18); + + // Use memory read multiple + pci_write_config8(dev, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + enables = pci_read_config8(dev, 0x9); + printk_debug("enables in reg 0x9 0x%x\n", enables); + + enables &= ~0x5; + + pci_write_config8(dev, 0x9, enables); + enables = pci_read_config8(dev, 0x9); + printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + enables = pci_read_config8(dev, 0x4); + printk_debug("command in reg 0x4 0x%x\n", enables); + enables |= 5; + + // No need for stepping - kevinh@ispiri.com + //enables &= ~0x80; + + pci_write_config8(dev, 0x4, enables); + enables = pci_read_config8(dev, 0x4); + printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + + pci_write_config32(dev, 0x10, 0x0); + pci_write_config32(dev, 0x14, 0x0); + pci_write_config32(dev, 0x18, 0x0); + pci_write_config32(dev, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config8(dev, 0x3d, 0x0); + pci_write_config8(dev, 0x3c, 0xff); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_1, +}; Index: src/southbridge/via/vt8237r/TODO =================================================================== --- src/southbridge/via/vt8237r/TODO (revision 0) +++ src/southbridge/via/vt8237r/TODO (revision 0) @@ -0,0 +1,26 @@ +NB & SB + +Fix DMA to 0xe0000-0xeffff - done +Move NB APIC init to NB code - done +MMCONFIG for PCI is reserved but not propagated (0xe0000000) - done +HPET is disabled - fixed + + +Motherboard code: +Fix reboot + + +K8 CODE: + +Fix the 2 dimms memory +Fix the resource typo + + +Fix enable more than 512KB flash chip +Fix HPET acpi record to match the ACPI reported table +Fix the e820 reserved region for MMCONFIG +Fix PCIe startup - done + +Fix error conditiion when PCIe Link is not trained correctly. +Disable GART in NB? + Index: src/southbridge/via/vt8237r/vt8237r.h =================================================================== --- src/southbridge/via/vt8237r/vt8237r.h (revision 0) +++ src/southbridge/via/vt8237r/vt8237r.h (revision 0) @@ -0,0 +1,19 @@ +//GPL here + +/* TODO: Some of these probably aren't needed. Find and eliminate */ +#if 0 //bad idea? pata moves to f0 if sata is disabled +const struct vt8237r { /* Function */ /* PCI ID */ + device_t .d15f0, /* SATA Controller */ /* 0x3149 */ + .d15f1, /* PATA Controller */ /* 0x0571 */ + .d16f0, /* USB 1.1 UHCI Ports 0-1 */ /* 0x3038 */ + .d16f1, /* USB 1.1 UHCI Ports 2-3 */ /* 0x3038 */ + .d16f2, /* USB 1.1 UHCI Ports 4-5 */ /* 0x3038 */ + .d16f3, /* USB 1.1 UHCI Ports 6-7 */ /* 0x3038 */ + .d16f4, /* USB 2.0 EHCI Ports 0-7 */ /* 0x3104 */ + .d16f5, /* USB 2.0 Communications */ /* 0xd104 */ + .d17f0, /* Bus Control and PM */ /* 0x3074 */ + .d17f5, /* AC97 Audio Codec */ /* 0x3059 */ + .d17f6, /* MC97 Modem Codec */ /* 0x3068 */ + .d18f0; /* VIA LAN Controller */ /* 0x3065 */ +} +#endif Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 0) +++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 0) @@ -0,0 +1,251 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SMBUS_IO_BASE 0x0400 //static + +/* With this, is SMBUS_IO_BASE added during compile or runtime? */ +#define SMBHSTSTAT SMBUS_IO_BASE + 0x0 +#define SMBSLVSTAT SMBUS_IO_BASE + 0x1 +#define SMBHSTCTL SMBUS_IO_BASE + 0x2 +#define SMBHSTCMD SMBUS_IO_BASE + 0x3 +#define SMBXMITADD SMBUS_IO_BASE + 0x4 +#define SMBHSTDAT0 SMBUS_IO_BASE + 0x5 +/* Rest of these aren't used... */ +#define SMBHSTDAT1 SMBUS_IO_BASE + 0x6 +#define SMBBLKDAT SMBUS_IO_BASE + 0x7 +#define SMBSLVCTL SMBUS_IO_BASE + 0x8 +#define SMBTRNSADD SMBUS_IO_BASE + 0x9 +#define SMBSLVDATA SMBUS_IO_BASE + 0xa +#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe +#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf + +/* Define register settings */ +#define HOST_RESET 0xff +#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ + +#define SMBUS_TIMEOUT (100*1000*10) + +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + +/* Debugging macros. Only necessary if something isn't working right */ + + +//#define DEBUG_SMBUS = 1 + +#ifdef DEBUG_SMBUS +#define PRINT_DEBUG(x) print_debug(x) +#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) +#else +#define PRINT_DEBUG(x) +#define PRINT_DEBUG_HEX16(x) +#endif + +/* TODO: datasheet link here */ + +/* See datasheet pages 125 and 137-139 */ + + +/* Internal functions */ + +/* TODO: make define? */ +#define SMBUS_DELAY() outb(0x80, 0x80) + +static void smbus_print_error(unsigned char host_status_register, int loops) +{ + /* Check if there actually was an error */ + if ( host_status_register == 0x00 || host_status_register == 0x40 || + host_status_register == 0x42) return; +// print_err("smbus_error: "); +// print_err_hex8(host_status_register); +// print_err("Wait was \r\n"); +// print_err_hex8(loops); + print_err("\r\n"); + if (loops >= SMBUS_TIMEOUT) { + print_err("SMBus Timout\r\n"); + } + if (host_status_register & (1 << 4)) { + print_err("Interrup/SMI# was Failed Bus Transaction\r\n"); + } + if (host_status_register & (1 << 3)) { + print_err("Bus Error\r\n"); + } + if (host_status_register & (1 << 2)) { + print_err("Device Error\r\n"); + } + if (host_status_register & (1 << 1)) { + print_err("Interrupt/SMI# was Successful Completion\r\n"); + } + if (host_status_register & (1 << 0)) { + print_err("Host Busy\r\n"); + } +} + +static void smbus_wait_until_ready(void) +{ + int loops; + + PRINT_DEBUG("Waiting until smbus ready\r\n"); + + loops = 0; + /* Yes, this is a mess, but it's the easiest way to do it */ + while((inb(SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT) + ++loops; + smbus_print_error(inb(SMBHSTSTAT), loops); +} + +static void smbus_reset(void) +{ + /* four resets? a little overboard? or just frustrated? */ + outb(HOST_RESET, SMBHSTSTAT); +#if 0 + outb(HOST_RESET, SMBHSTSTAT); + outb(HOST_RESET, SMBHSTSTAT); + outb(HOST_RESET, SMBHSTSTAT); +#endif + /* Datasheet says we have to read it to take ownership of SMBus */ + inb(SMBHSTSTAT); + + PRINT_DEBUG("After reset status: "); + PRINT_DEBUG_HEX16( inb(SMBHSTSTAT)); + PRINT_DEBUG("\r\n"); + +} + +/* Public functions */ + +static unsigned int get_spd_data(unsigned int dimm, unsigned int offset) +{ + unsigned int val; + + print_debug("DIMM "); + print_debug_hex8(dimm); + print_debug(" OFFSET "); + print_debug_hex8(offset); + print_debug("\r\n"); + + smbus_reset(); + /* clear host data port */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + /* Do some mathmatic magic */ + dimm = (dimm << 1); +// dimm &= 0x0E; +// dimm |= 0xA1; + dimm |= 1; + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + outb(0x48, SMBHSTCTL); + + SMBUS_DELAY(); + + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + print_debug("Read: "); + print_debug_hex8(val); + print_debug("\r\n"); + + smbus_reset(); /* probably don't have to do this, but it can't hurt */ + return val; /* can I just "return inb(SMBHSTDAT0)"? */ +} + +static unsigned int smbus_read_byte(unsigned int dimm, unsigned int offset) +{ + unsigned int data; + data = get_spd_data(dimm, offset); + return data; +} + +/* Debugging Function */ + +#ifdef DEBUG_SMBUS +static void dump_spd_data(void) +{ + int dimm, offset, regs; + unsigned int val; + + for(dimm = 0; dimm < 8; dimm++) + { + print_debug("SPD Data for DIMM "); + print_debug_hex8(dimm); + print_debug("\r\n"); + + val = get_spd_data(dimm, 0); + if(val == 0xff) + { + regs = 256; + } else if(val == 0x80) { + regs = 128; + } else { + print_debug("No DIMM present\r\n"); + regs = 0; + } + + for(offset = 0; offset < regs; offset++) + { + print_debug(" Offset "); + print_debug_hex8(offset); + print_debug(" = 0x"); + print_debug_hex8(get_spd_data(0x50 + dimm, offset)); + print_debug("\r\n"); + } + } +} +#else +#define dump_spd_data() +#endif + + +static void enable_smbus(void) +{ + int c; + device_t dev; + + /* Power management controller */ + /* This should work, but there are more important things to work on */ + /* dev = PCI_DEV(0, 0x11, 0); */ + + dev = pci_locate_device(PCI_ID(0x1106, 0x3227), 0); + + if (dev == PCI_DEV_INVALID) + { + die("Power Managment Controller not found\r\n"); + } + + /* Set clock source */ + pci_write_config8(dev, 0x94, 0xa0); + + /* Write SMBus IO base to 0xd0, and enable SMBus */ + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); + + /* Set to Award value */ + pci_write_config8(dev, 0xd2, 0x01); + + /* make it work for I/O ...*/ + pci_write_config16(dev, 0x04, 0x0001); + + /* The other, slightly hackish, fixup method */ + for(c = 0; c < 30; c++) get_spd_data(0x50, c); +} + Index: src/southbridge/via/vt8237r/romstrap.lds =================================================================== --- src/southbridge/via/vt8237r/romstrap.lds (revision 0) +++ src/southbridge/via/vt8237r/romstrap.lds (revision 0) @@ -0,0 +1,28 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +SECTIONS { + . = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +} Index: src/southbridge/via/vt8237r/vt8237r_sata.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_sata.c (revision 0) +++ src/southbridge/via/vt8237r/vt8237r_sata.c (revision 0) @@ -0,0 +1,56 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "vt8237r.h" + +static void sata_init(struct device *dev) +{ + uint8_t reg; + + printk_debug("Configuring VIA SATA Controller\n"); + + /* class IDE Disk */ + reg = pci_read_config8(dev, 0x45); + reg &= 0x7f; /* Sub Class Write Protect off */ + pci_write_config8(dev, 0x45, reg); + pci_write_config8(dev, 0xa, 0x1); + reg |= 0x80; /* Sub Class Write Protect on */ + pci_write_config8(dev, 0x45, reg); + +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = 0, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x3149, +}; Index: src/southbridge/via/vt8237r/chip.h =================================================================== --- src/southbridge/via/vt8237r/chip.h (revision 0) +++ src/southbridge/via/vt8237r/chip.h (revision 0) @@ -0,0 +1,21 @@ +#ifndef _SOUTHBRIDGE_VIA_VT8237R +#define _SOUTHBRIDGE_VIA_VT8237R + +extern struct chip_operations southbridge_via_vt8237r_ops; + +struct southbridge_via_vt8237r_config { + /* PCI function enables */ + /* i.e. so that pci scan bus will find them. */ + /* I am putting in IDE as an example but obviously this needs + * to be more complete! + */ + int enable_ide; + /* enables of functions of devices */ + /* USB removed, code comments essentially said it should have been long ago */ + int enable_native_ide; + /* No serial on vt8237 */ + int enable_keyboard; + int enable_nvram; +}; + +#endif /* _SOUTHBRIDGE_VIA_VT8237R */ Index: src/southbridge/via/vt8237r/vt8237r_nic.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_nic.c (revision 0) +++ src/southbridge/via/vt8237r/vt8237r_nic.c (revision 0) @@ -0,0 +1,40 @@ +#include +#include +#include +#include +#include +#include "vt8237r.h" + +/* + * Enable the ethernet device and turn off stepping (because it is integrated + * inside the southbridge) + */ +/* The PCI ID for this for vt8237 matches vt8235. I'm not bothering to mess + * with it for now, and hoping it works */ + +static void nic_init(struct device *dev) +{ + uint8_t byte; + + printk_debug("Configuring VIA Rhine LAN\n"); + + /* We don't need stepping - though the device supports it */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .enable = 0, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8233_7, +}; Index: src/southbridge/via/vt8237r/vt8237_bridge.c =================================================================== --- src/southbridge/via/vt8237r/vt8237_bridge.c (revision 0) +++ src/southbridge/via/vt8237r/vt8237_bridge.c (revision 0) @@ -0,0 +1,59 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void smth_enable(struct device *dev) { + +// print_err("B188 device dump\n"); + + writeback(dev, 0x40, 0x91); + writeback(dev, 0x41, 0x40); + writeback(dev, 0x43, 0x44); + writeback(dev, 0x44, 0x31); + writeback(dev, 0x45, 0x3a); + writeback(dev, 0x46, 0x88); + writeback(dev, 0x47, 0xb1); + writeback(dev, 0x3e, 0x16); //bridge control???? + + dump_south(dev); + + +} + +static struct device_operations smth_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = smth_enable, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &smth_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0xb188, +}; Index: src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_lpc.c (revision 0) +++ src/southbridge/via/vt8237r/vt8237r_lpc.c (revision 0) @@ -0,0 +1,335 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Based on other VIA SB code. + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "vt8237r.h" +#include "chip.h" + + +#include + + +struct ioapicreg { + unsigned int reg; + unsigned int value_low, value_high; +}; + + +extern void dump_south(device_t dev0); + +static struct ioapicreg ioapicregvalues[] = { +#define ALL (0xff << 24) +#define NONE (0) +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + /* IO-APIC virtual wire mode configuration */ + /* mask, trigger, polarity, destination, delivery, vector */ + { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, + { 1, DISABLED, NONE}, + { 2, DISABLED, NONE}, + { 3, DISABLED, NONE}, + { 4, DISABLED, NONE}, + { 5, DISABLED, NONE}, + { 6, DISABLED, NONE}, + { 7, DISABLED, NONE}, + { 8, DISABLED, NONE}, + { 9, DISABLED, NONE}, + { 10, DISABLED, NONE}, + { 11, DISABLED, NONE}, + { 12, DISABLED, NONE}, + { 13, DISABLED, NONE}, + { 14, DISABLED, NONE}, + { 15, DISABLED, NONE}, + { 16, DISABLED, NONE}, + { 17, DISABLED, NONE}, + { 18, DISABLED, NONE}, + { 19, DISABLED, NONE}, + { 20, DISABLED, NONE}, + { 21, DISABLED, NONE}, + { 22, DISABLED, NONE}, + { 23, DISABLED, NONE}, + /* Be careful and don't write past the end... */ +}; + + + +static void setup_ioapic(unsigned long ioapic_base) +{ + int i; + unsigned long value_low, value_high, adr; + volatile unsigned long *l; + struct ioapicreg *a = ioapicregvalues; + + //delivered to CPU0 + ioapicregvalues[0].value_high = (lapicid())<<(56-32); + + l = (unsigned long *) ioapic_base; + + l[0] = 3; //set APIC to FSB message + adr = l[4]; + l[4] = (adr & 0xFFFFFE) | 1; + l[0] = 0; //set APIC ADDR - this will be APIC 2 + adr = l[4]; + l[4] = (adr & 0xF0FFFF) | (2<<24); + + for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + i++, a++) { + l[0] = (a->reg * 2) + 0x10; + l[4] = a->value_low; + value_low = l[4]; + l[0] = (a->reg *2) + 0x11; + l[4] = a->value_high; + value_high = l[4]; + if ((i==0) && (value_low == 0xffffffff)) { + printk_warning("IO APIC not responding.\n"); + return; + } + } +} + + +static void pci_routing_fixup(struct device *dev) +{ + + /* set up PCI IRQ routing, route everything through APIC */ + pci_write_config8(dev, 0x44, 0x00); /* PCI PNP Interrupt Routing INTE/F - disable */ + pci_write_config8(dev, 0x45, 0x00); /* PCI PNP Interrupt Routing INTG/H - disable */ + pci_write_config8(dev, 0x46, 0x10); /* Route INTE-INTH through registers above, no map to INTA-INTD */ + + pci_write_config8(dev, 0x54, 0x00); /* PCI Interrupt Polarity */ + pci_write_config8(dev, 0x55, 0x00); /* PCI INTA# Routing */ + pci_write_config8(dev, 0x56, 0x00); /* PCI INTB#/C# Routing */ + pci_write_config8(dev, 0x57, 0x00); /* PCI INTD# Routing */ +} + +/* + * Set up the power management capabilities directly into ACPI mode. This + * avoids having to handle any System Management Interrupts (SMI's) which I + * can't figure out how to do !!!! + */ + +void setup_pm(device_t dev) +{ + + // Set gen config 0 + pci_write_config8(dev, 0x80, 0x20); + + // Set ACPI base address to IO 0x500 + pci_write_config16(dev, 0x88, 0x501); + + // set ACPI irq to 9, need to set IRQ 9 override to level! + pci_write_config8(dev, 0x82, 0x49); + + // primary interupt channel + pci_write_config16(dev, 0x84, 0x30b2); + + // throttle / stop clock control + pci_write_config8(dev, 0x8d, 0x18); + + pci_write_config8(dev, 0x93, 0x88); + pci_write_config8(dev, 0x94, 0xa4); + pci_write_config8(dev, 0x95, 0xcc); + pci_write_config8(dev, 0x98, 0); + pci_write_config8(dev, 0x99, 0x1e); //?? + + /* enable SATA LED, disable CPU Frequency Change */ + pci_write_config8(dev, 0xe5, 0x9); + + /* REQ5 as PCI request input - should be together with INTE-INTH*/ + + pci_write_config8(dev, 0xe4, 0x4); + + // Enable ACPI access (and setup like award) + pci_write_config8(dev, 0x81, 0x84); + + outw(0xffff, 0x500); + outw(0xffff, 0x520); + outw(0xffff, 0x528); + outl(0xffffffff, 0x530); + + outw(0x0, 0x524); + outw(0x0, 0x52a); + outw(0x0, 0x52c); + outl(0x0, 0x534); + outl(0x0, 0x538); //fix + outb(0x0, 0x542); + outw(0x001, 0x504); +} + +static void vt8237r_init(struct device *dev) +{ + unsigned char enables, byte; + + printk_debug("vt8237r init\n"); + + byte = pci_read_config8(dev, PCI_COMMAND); + byte |= PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); + + + // enable the internal I/O decode + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + //FIXME Map 4MB of FLASH into the address space + pci_write_config8(dev, 0x41, 0x0); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev, 0x40); + enables |= 0x44; + pci_write_config8(dev, 0x40, enables); + + // Set 0x42 to 0xf8 to match Award bios + enables = pci_read_config8(dev, 0x42); + enables |= 0xf8; + pci_write_config8(dev, 0x42, enables); + + + /* Delay Transaction Control */ + pci_write_config8(dev, 0x43, 0xb); + + /* IO Recovery time */ + pci_write_config8(dev, 0x4c, 0x44); + + /* ROM Memory Cycles Go To LPC */ + pci_write_config8(dev, 0x59, 0x80); + + /* bypass Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI */ + pci_write_config8(dev, 0x5B, 0xb); + + /* set Read Pass Write Control Enable (force A2 from APIC FSB to low)*/ + pci_write_config8(dev, 0x48, 0x8c); + + /* Set 0x58 to 0x43 APIC and RTC*/ + pci_write_config8(dev, 0x58, 0x43); + + /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + //pci_write_config8(dev, 0x4f, enables); + + /* enable serial irq */ + pci_write_config8(dev, 0x52, 0x9); + + + + /* dma */ + //pci_write_config8(dev, 0x53, 0x00); + + //enable HPET, ACPI has define to fixed addr +#define HPET_ADDR 0xfed00000ULL + + pci_write_config16(dev, 0x69, ((HPET_ADDR >> 10) & 0xffff) ); + pci_write_config8(dev, 0x6b, ((HPET_ADDR >> 26) & 0x3f) ); + pci_write_config8(dev, 0x68, 0x80); + + // Power management setup + setup_pm(dev); + + // Start the rtc + rtc_init(0); +} + +void vt8237r_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + /* fixed APIC resource */ + res = new_resource(dev, 0x44); + res->base = 0xfec00000; + res->size = 256; + res->limit = res->base + res->size -1; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +void vt8237r_enable_resources(device_t dev) +{ + + /* vt8237r is not a pci bridge and has no resources of its own (other than standard PC i/o addresses) + however it does control the isa bus and so we need to manually call enable childrens resources on that bus */ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); + +} + +static void keyboard_on(struct device *dev) +{ + unsigned char regval; + + regval = pci_read_config8(dev, 0x51); + regval |= 0x05; + regval &= 0xfd; + pci_write_config8(dev, 0x51, regval); + + init_pc_keyboard(0x60, 0x64, 0); +} + + +static void southbridge_init(struct device *dev) +{ + unsigned int v; + vt8237r_init(dev); + pci_routing_fixup(dev); + setup_ioapic(0xfec00000); + setup_i8259(); + keyboard_on(dev); + + //dump_south(dev); +} + +static struct device_operations vt8237r_lpc_ops = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = vt8237r_enable_resources, + .init = &southbridge_init, + .scan_bus = scan_static_bus, +}; + +static struct pci_driver lpc_driver __pci_driver = { + .ops = &vt8237r_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x3227, +}; Index: src/southbridge/via/k8t890/Config.lb =================================================================== --- src/southbridge/via/k8t890/Config.lb (revision 0) +++ src/southbridge/via/k8t890/Config.lb (revision 0) @@ -0,0 +1,6 @@ +driver k8t890_ctrl.o +driver k8t890_dram.o +driver k8t890_host.o +driver k8t890_host_ctrl.o +driver k8t890_pcie.o +driver k8t890_traf_ctrl.o Index: src/southbridge/via/k8t890/k8t890_host.c =================================================================== --- src/southbridge/via/k8t890/k8t890_host.c (revision 0) +++ src/southbridge/via/k8t890/k8t890_host.c (revision 0) @@ -0,0 +1,43 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void host_enable(struct device *dev) { + /* multiple function control */ + pci_write_config8(dev, 0x4f, 0x01); +} + +static struct device_operations host_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &host_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x238, +}; Index: src/southbridge/via/k8t890/k8t890_pcie.c =================================================================== --- src/southbridge/via/k8t890/k8t890_pcie.c (revision 0) +++ src/southbridge/via/k8t890/k8t890_pcie.c (revision 0) @@ -0,0 +1,159 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +//#include +#include +#include +#include + +void peg_init(struct device *dev) +{ + uint8_t reg; + + printk_debug("Configuring PCIe PEG\n"); + dump_south(dev); + + +// reg = pci_read_config8(dev, 0xe0); +// pci_write_config8(dev, 0xe0, (reg & 0xf0) | 0xc); + + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); //disable link + + pci_write_config8(dev, 0xe1, 0xb); //award has 0xb VIA recomends 0x4 + + //pci_write_config8(dev, 0xe2, 0x0); + //pci_write_config8(dev, 0xe3, 0x92); + + pci_write_config8(dev, 0xc0, 0x43); //disable scrambling bit 6 to 1 + + pci_write_config8(dev, 0xb1, 0xf0); //set replay timer limit + + reg = pci_read_config8(dev, 0xb8); + pci_write_config8(dev, 0xb8, reg | 0x1); // bit0=1 SDP (Start DLLP) always at Lane0. + + reg = pci_read_config8(dev, 0xa4); + pci_write_config8(dev, 0xa4, reg | 0x30); //set downstream wait and Upstream Checking Malformed TLP through "Byte Enable Rule" And "Over 4K Boundary Rule" + + + + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); //enable link + + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x20); //retrain link + + + reg = pci_read_config8(dev, 0x3e); + reg |= 0x40; + pci_write_config8(dev, 0x3e, reg); //bus reset + reg = pci_read_config8(dev, 0x3e); + reg &= ~0x40; + pci_write_config8(dev, 0x3e, reg); //bus reset done + + dump_south(dev); +} + + +void pcie_init(struct device *dev) +{ + uint8_t reg; + + printk_debug("Configuring PCIe PEXs\n"); + dump_south(dev); + + +// reg = pci_read_config8(dev, 0xe0); +// pci_write_config8(dev, 0xe0, (reg & 0xf0) | 0xc); + + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); //disable link + + pci_write_config8(dev, 0xe1, 0xb); //award has 0xb VIA recomends 0x4 + pci_write_config8(dev, 0xb1, 0xf0); //set replay timer limit + + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); //enable link + + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x20); //retrain link + + reg = pci_read_config8(dev, 0x3e); + reg |= 0x40; + pci_write_config8(dev, 0x3e, reg); //bus reset + reg = pci_read_config8(dev, 0x3e); + reg &= ~0x40; + pci_write_config8(dev, 0x3e, reg); //bus reset done + + dump_south(dev); +} + + +static struct device_operations peg_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = peg_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &peg_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0xa238, +}; + +static struct pci_driver pcie_drvd3f0 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0xc238, +}; + +static struct pci_driver pcie_drvd3f1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0xd238, +}; + +static struct pci_driver pcie_drvd3f2 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0xe238, +}; + +static struct pci_driver pcie_drvd3f3 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0xf238, +}; Index: src/southbridge/via/k8t890/k8t890_traf_ctrl.c =================================================================== --- src/southbridge/via/k8t890/k8t890_traf_ctrl.c (revision 0) +++ src/southbridge/via/k8t890/k8t890_traf_ctrl.c (revision 0) @@ -0,0 +1,112 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +void mmconfig_set_resources(device_t dev) { + + struct resource *resource; + uint8_t reg; + + resource = find_resource(dev, 0x61); + if (resource) { + report_resource_stored(dev, resource, ""); + + /* Remember this resource has been stored */ + resource->flags |= IORESOURCE_STORED; + pci_write_config8(dev, 0x61, (resource->base >> 28)); + reg = pci_read_config8(dev, 0x60); + reg |=0x3; + /* enable MMCONFIG decoding */ + pci_write_config8(dev, 0x60, reg); + } + + pci_dev_set_resources(dev); +} + + + +static void apic_mmconfig_read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, 0x40); + /* NB APIC fixed to this addr */ + res->base = 0xfecc0000; + res->size = 256; + res->limit = res->base + res->size -1; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Add a MMCONFIG resource */ + res = new_resource(dev, 0x61); + res->size = 256*1024*1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void traf_ctrl_enable(struct device *dev) { + volatile unsigned long * apic; + unsigned long data; + + writeback(dev, 0x60, 0x88); //enable D3F1-D3F3, no device2 redirect, enable just one device behind bridge device 2 and device 3) */ + //will enable MMCONFIG later + writeback(dev, 0x64, 0x23); + writeback(dev, 0x62, 0x00); /* no extended RCRB Base Address */ + + //offset80 ->95 bit 4 in 1 in award + + //enable APIC, to 0xfecc0000 + writeback(dev, 0x40, 0x8c); + writeback(dev, 0x41, 0x00); + //BT_INTR enable, APIC Nonshare Mode Enable + writeback(dev, 0x42, 0x5); + apic = (unsigned long *) 0xfecc0000; + + apic[0] = 3; //set APIC to FSB message + data = apic[4]; + apic[4] = (data & 0xFFFFFE) | 1; + + apic[0] = 0; //set APIC ADDR + data = apic[4]; + apic[4] = (data & 0xF0FFFF) | (3<<24); //APIC ID 3 +} + +static struct device_operations traf_ctrl_ops = { + .read_resources = apic_mmconfig_read_resources, + .set_resources = mmconfig_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = traf_ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &traf_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x5238, +}; Index: src/southbridge/via/k8t890/k8t890_host_ctrl.c =================================================================== --- src/southbridge/via/k8t890/k8t890_host_ctrl.c (revision 0) +++ src/southbridge/via/k8t890/k8t890_host_ctrl.c (revision 0) @@ -0,0 +1,73 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void host_ctrl_enable(struct device *dev) { + + + dump_south(dev); + writeback(dev, 0xa0, 0x13); //bit4 is reserved! + writeback(dev, 0xa1, 0x8e); //some bits are reserved + writeback(dev, 0xa2, 0x0e); //IO NVRAM base 0xe00-0xeff disabled + writeback(dev, 0xa3, 0x31); + writeback(dev, 0xa4, 0x30); + + writeback(dev, 0xa5, 0x3c); //some bits reserved + writeback(dev, 0xa6, 0x80); //some bits reserved + writeback(dev, 0xa7, 0x86); //some bits reserved + writeback(dev, 0xa8, 0x7f); //some bits reserved + writeback(dev, 0xa9, 0xcf); //some bits reserved + writeback(dev, 0xaa, 0x44); + writeback(dev, 0xab, 0x22); + writeback(dev, 0xac, 0x35); //maybe bit0 is readonly? + + writeback(dev, 0xae, 0x22); + writeback(dev, 0xaf, 0x40); +//b0 is missing + writeback(dev, 0xb1, 0x13); + writeback(dev, 0xb4, 0x02); //some bits are reserved + writeback(dev, 0xc0, 0x20); + writeback(dev, 0xc1, 0xaa); + writeback(dev, 0xc2, 0xaa); + writeback(dev, 0xc3, 0x02); + writeback(dev, 0xc4, 0x50); + writeback(dev, 0xc5, 0x50); + dump_south(dev); + + +} + +static struct device_operations host_ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &host_ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x2238, +}; Index: src/southbridge/via/k8t890/k8t890_dram.c =================================================================== --- src/southbridge/via/k8t890/k8t890_dram.c (revision 0) +++ src/southbridge/via/k8t890/k8t890_dram.c (revision 0) @@ -0,0 +1,70 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + + +static void dram_enable(struct device *dev) { + + writeback(dev, 0x86, 0x39); /* enable Lowest Interrupt arbitration for APIC, + enable NB APIC decoding, MSI support, no SMRAM, + compatible SMM */ + + writeback(dev, 0x80, 0xff); //no shadows for C ROM + writeback(dev, 0x81, 0xff); //no shadows for D ROM + writeback(dev, 0x82, 0xff); //no shadows for E ROM + writeback(dev, 0x83, 0x30); //no shadows for F ROM + + { + //FIXME AMD64SPECIC, need to know the end of memory! + msr_t msr; + u16 reg; + msr = rdmsr(TOP_MEM); + reg = pci_read_config16(dev, 0x84); + reg&= 0xf; + pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg ); + + reg = pci_read_config16(dev, 0x88); + reg&= 0xf800; + + pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg ); + + } + +} + +static struct device_operations dram_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = dram_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &dram_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x3238, +}; Index: src/southbridge/via/k8t890/k8t890_ctrl.c =================================================================== --- src/southbridge/via/k8t890/k8t890_ctrl.c (revision 0) +++ src/southbridge/via/k8t890/k8t890_ctrl.c (revision 0) @@ -0,0 +1,105 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static void ctrl_enable(struct device *dev) { + + print_err("7238 device dump\n"); +// +//Note: PCI1_RxXX[6] and PCI1_RxYY[0] should be set to 1 to fix V-Link ordering issue for VT8237R +//Plus. + //C2P Read ACK Return Priority + //1: Address bit[27:24] are used as extended register address bit[11:8] + writeback(dev, 0x47, 0x30); + //Program V-link 8X 16bit full duplex, this needs to be fixed for other than VT8237R SB + writeback(dev, 0x48, 0x23); + + //70: c2 c8 ee 01 24 0f 50 08 01 00 00 00 7f 00 00 02 + //70: 00 48 00 00 01 00 00 00 01 00 00 00 00 00 12 02 + //magic init this not well documented :/ + + writeback(dev, 0x70, 0xc2); + + // PCI Control + writeback(dev, 0x72, 0xee); + writeback(dev, 0x73, 0x01); + writeback(dev, 0x74, 0x24); + writeback(dev, 0x75, 0x0f); + writeback(dev, 0x76, 0x50); + writeback(dev, 0x77, 0x08); + writeback(dev, 0x78, 0x01); + //APIC on HT etc etc + writeback(dev, 0x7c, 0x7f); + writeback(dev, 0x7f, 0x02); + + //WARNING NEED to copy some registers from NB (D0F3) to SB (D0F7) + { + device_t devFUNNB3 = dev_find_device(PCI_VENDOR_ID_VIA, 0x3238, 0); + u8 regm, regm2, regm3; + + //shadow CTRL + regm = pci_read_config8(devFUNNB3,0x88); + writeback(dev, 0x57, regm); + + //shadow page C + regm = pci_read_config8(devFUNNB3,0x80); + writeback(dev, 0x61, regm); + + //shadow page D + regm = pci_read_config8(devFUNNB3,0x81); + writeback(dev, 0x62, regm); + + //SMM and APIC decoding + regm = pci_read_config8(devFUNNB3,0x86); + writeback(dev, 0xe6, regm); + + //shadow page E + regm3 = pci_read_config8(devFUNNB3,0x82); + //writeback(dev, 0xe6, regm); + if (regm3 == 0xff) + regm3 = 0xC0; + else + regm3 = 0x0; //all access bits for 0xE0000-0xEFFFF encode as just 2 bits! and write them to 0x63 7-6 + //but! VIA 8237A has the mirror at 0x64! + + // page F + Memhole copy + regm = pci_read_config8(devFUNNB3,0x83); + pci_write_config8(dev,0x63, regm3 | (regm & 0x3F)); + } + +} + +static struct device_operations ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = ctrl_enable, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x7238, +}; Index: src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- src/cpu/x86/lapic/lapic_cpu_init.c (revision 2776) +++ src/cpu/x86/lapic/lapic_cpu_init.c (working copy) @@ -60,7 +60,7 @@ * Starting actual IPI sequence... */ - printk_spew("Asserting INIT.\n"); + printk_err("Asserting INIT. on %x\n", apicid); /* * Turn INIT on target chip Index: src/mainboard/asus/a8v/dsdt.c =================================================================== --- src/mainboard/asus/a8v/dsdt.c (revision 0) +++ src/mainboard/asus/a8v/dsdt.c (revision 0) @@ -0,0 +1,153 @@ +/* + * + * Intel ACPI Component Architecture + * ASL Optimizing Compiler version 20061109 [May 15 2007] + * Copyright (C) 2000 - 2006 Intel Corporation + * Supports ACPI Specification Revision 3.0a + * + * Compilation of "dsdt.asl" - Sat Sep 15 15:32:50 2007 + * + * C source code output + * + */ +unsigned char AmlCode[] = +{ + 0x44,0x53,0x44,0x54,0x4E,0x04,0x00,0x00, /* 00000000 "DSDTN..." */ + 0x01,0x80,0x4C,0x58,0x42,0x49,0x4F,0x53, /* 00000008 "..LXBIOS" */ + 0x4C,0x58,0x42,0x2D,0x44,0x53,0x44,0x54, /* 00000010 "LXB-DSDT" */ + 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */ + 0x09,0x11,0x06,0x20,0x10,0x1F,0x5F,0x50, /* 00000020 "... .._P" */ + 0x52,0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55, /* 00000028 "R_[..CPU" */ + 0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x5B, /* 00000030 "0......[" */ + 0x83,0x0B,0x43,0x50,0x55,0x31,0x01,0x00, /* 00000038 "..CPU1.." */ + 0x00,0x00,0x00,0x00,0x08,0x5F,0x53,0x30, /* 00000040 "....._S0" */ + 0x5F,0x12,0x06,0x04,0x00,0x00,0x00,0x00, /* 00000048 "_......." */ + 0x08,0x5F,0x53,0x35,0x5F,0x12,0x08,0x04, /* 00000050 "._S5_..." */ + 0x0A,0x02,0x0A,0x02,0x00,0x00,0x10,0x4F, /* 00000058 ".......O" */ + 0x3E,0x5F,0x53,0x42,0x5F,0x5B,0x82,0x47, /* 00000060 ">_SB_[.G" */ + 0x3E,0x50,0x43,0x49,0x30,0x08,0x5F,0x48, /* 00000068 ">PCI0._H" */ + 0x49,0x44,0x0C,0x41,0xD0,0x0A,0x03,0x08, /* 00000070 "ID.A...." */ + 0x5F,0x41,0x44,0x52,0x00,0x08,0x5F,0x55, /* 00000078 "_ADR.._U" */ + 0x49,0x44,0x00,0x08,0x5F,0x42,0x42,0x4E, /* 00000080 "ID.._BBN" */ + 0x00,0x08,0x5F,0x50,0x52,0x54,0x12,0x44, /* 00000088 ".._PRT.D" */ + 0x15,0x1B,0x12,0x0B,0x04,0x0C,0xFF,0xFF, /* 00000090 "........" */ + 0x0B,0x00,0x00,0x00,0x0A,0x10,0x12,0x0B, /* 00000098 "........" */ + 0x04,0x0C,0xFF,0xFF,0x0B,0x00,0x01,0x00, /* 000000A0 "........" */ + 0x0A,0x11,0x12,0x0C,0x04,0x0C,0xFF,0xFF, /* 000000A8 "........" */ + 0x0B,0x00,0x0A,0x02,0x00,0x0A,0x12,0x12, /* 000000B0 "........" */ + 0x0C,0x04,0x0C,0xFF,0xFF,0x0B,0x00,0x0A, /* 000000B8 "........" */ + 0x03,0x00,0x0A,0x13,0x12,0x0B,0x04,0x0C, /* 000000C0 "........" */ + 0xFF,0xFF,0x0C,0x00,0x00,0x00,0x0A,0x11, /* 000000C8 "........" */ + 0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x0C,0x00, /* 000000D0 "........" */ + 0x01,0x00,0x0A,0x12,0x12,0x0C,0x04,0x0C, /* 000000D8 "........" */ + 0xFF,0xFF,0x0C,0x00,0x0A,0x02,0x00,0x0A, /* 000000E0 "........" */ + 0x13,0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x0C, /* 000000E8 "........" */ + 0x00,0x0A,0x03,0x00,0x0A,0x10,0x12,0x0B, /* 000000F0 "........" */ + 0x04,0x0C,0xFF,0xFF,0x0D,0x00,0x00,0x00, /* 000000F8 "........" */ + 0x0A,0x12,0x12,0x0B,0x04,0x0C,0xFF,0xFF, /* 00000100 "........" */ + 0x0D,0x00,0x01,0x00,0x0A,0x13,0x12,0x0C, /* 00000108 "........" */ + 0x04,0x0C,0xFF,0xFF,0x0D,0x00,0x0A,0x02, /* 00000110 "........" */ + 0x00,0x0A,0x10,0x12,0x0C,0x04,0x0C,0xFF, /* 00000118 "........" */ + 0xFF,0x0D,0x00,0x0A,0x03,0x00,0x0A,0x11, /* 00000120 "........" */ + 0x12,0x0B,0x04,0x0C,0x00,0x00,0x0F,0x00, /* 00000128 "........" */ + 0x01,0x00,0x0A,0x14,0x12,0x0B,0x04,0x0C, /* 00000130 "........" */ + 0x01,0x00,0x0F,0x00,0x00,0x00,0x0A,0x14, /* 00000138 "........" */ + 0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x10,0x00, /* 00000140 "........" */ + 0x00,0x00,0x0A,0x15,0x12,0x0B,0x04,0x0C, /* 00000148 "........" */ + 0xFF,0xFF,0x10,0x00,0x01,0x00,0x0A,0x15, /* 00000150 "........" */ + 0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x10,0x00, /* 00000158 "........" */ + 0x0A,0x02,0x00,0x0A,0x15,0x12,0x0C,0x04, /* 00000160 "........" */ + 0x0C,0xFF,0xFF,0x10,0x00,0x0A,0x03,0x00, /* 00000168 "........" */ + 0x0A,0x15,0x12,0x0C,0x04,0x0C,0xFF,0xFF, /* 00000170 "........" */ + 0x11,0x00,0x0A,0x02,0x00,0x0A,0x16,0x12, /* 00000178 "........" */ + 0x0B,0x04,0x0C,0xFF,0xFF,0x02,0x00,0x00, /* 00000180 "........" */ + 0x00,0x0A,0x1B,0x12,0x0B,0x04,0x0C,0xFF, /* 00000188 "........" */ + 0xFF,0x02,0x00,0x01,0x00,0x0A,0x1B,0x12, /* 00000190 "........" */ + 0x0C,0x04,0x0C,0xFF,0xFF,0x02,0x00,0x0A, /* 00000198 "........" */ + 0x02,0x00,0x0A,0x1B,0x12,0x0C,0x04,0x0C, /* 000001A0 "........" */ + 0xFF,0xFF,0x02,0x00,0x0A,0x03,0x00,0x0A, /* 000001A8 "........" */ + 0x1B,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x03, /* 000001B0 "........" */ + 0x00,0x00,0x00,0x0A,0x1F,0x12,0x0B,0x04, /* 000001B8 "........" */ + 0x0C,0xFF,0xFF,0x03,0x00,0x01,0x00,0x0A, /* 000001C0 "........" */ + 0x23,0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x03, /* 000001C8 "#......." */ + 0x00,0x0A,0x02,0x00,0x0A,0x27,0x12,0x0C, /* 000001D0 ".....'.." */ + 0x04,0x0C,0xFF,0xFF,0x03,0x00,0x0A,0x03, /* 000001D8 "........" */ + 0x00,0x0A,0x2B,0x5B,0x82,0x4F,0x04,0x50, /* 000001E0 "..+[.O.P" */ + 0x45,0x47,0x47,0x08,0x5F,0x41,0x44,0x52, /* 000001E8 "EGG._ADR" */ + 0x0C,0x00,0x00,0x02,0x00,0x08,0x5F,0x55, /* 000001F0 "......_U" */ + 0x49,0x44,0x00,0x08,0x5F,0x42,0x42,0x4E, /* 000001F8 "ID.._BBN" */ + 0x0A,0x02,0x08,0x5F,0x50,0x52,0x54,0x12, /* 00000200 "..._PRT." */ + 0x2C,0x04,0x12,0x09,0x04,0x0B,0xFF,0xFF, /* 00000208 ",......." */ + 0x00,0x00,0x0A,0x18,0x12,0x09,0x04,0x0B, /* 00000210 "........" */ + 0xFF,0xFF,0x01,0x00,0x0A,0x19,0x12,0x0A, /* 00000218 "........" */ + 0x04,0x0B,0xFF,0xFF,0x0A,0x02,0x00,0x0A, /* 00000220 "........" */ + 0x1A,0x12,0x0A,0x04,0x0B,0xFF,0xFF,0x0A, /* 00000228 "........" */ + 0x03,0x00,0x0A,0x1B,0x5B,0x82,0x4F,0x04, /* 00000230 "....[.O." */ + 0x50,0x45,0x58,0x30,0x08,0x5F,0x41,0x44, /* 00000238 "PEX0._AD" */ + 0x52,0x0C,0x00,0x00,0x03,0x00,0x08,0x5F, /* 00000240 "R......_" */ + 0x55,0x49,0x44,0x00,0x08,0x5F,0x42,0x42, /* 00000248 "UID.._BB" */ + 0x4E,0x0A,0x03,0x08,0x5F,0x50,0x52,0x54, /* 00000250 "N..._PRT" */ + 0x12,0x2C,0x04,0x12,0x09,0x04,0x0B,0xFF, /* 00000258 ".,......" */ + 0xFF,0x00,0x00,0x0A,0x1C,0x12,0x09,0x04, /* 00000260 "........" */ + 0x0B,0xFF,0xFF,0x01,0x00,0x0A,0x1D,0x12, /* 00000268 "........" */ + 0x0A,0x04,0x0B,0xFF,0xFF,0x0A,0x02,0x00, /* 00000270 "........" */ + 0x0A,0x1E,0x12,0x0A,0x04,0x0B,0xFF,0xFF, /* 00000278 "........" */ + 0x0A,0x03,0x00,0x0A,0x1F,0x5B,0x82,0x4F, /* 00000280 ".....[.O" */ + 0x04,0x50,0x45,0x58,0x31,0x08,0x5F,0x41, /* 00000288 ".PEX1._A" */ + 0x44,0x52,0x0C,0x01,0x00,0x03,0x00,0x08, /* 00000290 "DR......" */ + 0x5F,0x55,0x49,0x44,0x00,0x08,0x5F,0x42, /* 00000298 "_UID.._B" */ + 0x42,0x4E,0x0A,0x04,0x08,0x5F,0x50,0x52, /* 000002A0 "BN..._PR" */ + 0x54,0x12,0x2C,0x04,0x12,0x09,0x04,0x0B, /* 000002A8 "T.,....." */ + 0xFF,0xFF,0x00,0x00,0x0A,0x20,0x12,0x09, /* 000002B0 "..... .." */ + 0x04,0x0B,0xFF,0xFF,0x01,0x00,0x0A,0x21, /* 000002B8 ".......!" */ + 0x12,0x0A,0x04,0x0B,0xFF,0xFF,0x0A,0x02, /* 000002C0 "........" */ + 0x00,0x0A,0x22,0x12,0x0A,0x04,0x0B,0xFF, /* 000002C8 ".."....." */ + 0xFF,0x0A,0x03,0x00,0x0A,0x23,0x5B,0x82, /* 000002D0 ".....#[." */ + 0x4F,0x04,0x50,0x45,0x58,0x32,0x08,0x5F, /* 000002D8 "O.PEX2._" */ + 0x41,0x44,0x52,0x0C,0x02,0x00,0x03,0x00, /* 000002E0 "ADR....." */ + 0x08,0x5F,0x55,0x49,0x44,0x00,0x08,0x5F, /* 000002E8 "._UID.._" */ + 0x42,0x42,0x4E,0x0A,0x05,0x08,0x5F,0x50, /* 000002F0 "BBN..._P" */ + 0x52,0x54,0x12,0x2C,0x04,0x12,0x09,0x04, /* 000002F8 "RT.,...." */ + 0x0B,0xFF,0xFF,0x00,0x00,0x0A,0x24,0x12, /* 00000300 "......$." */ + 0x09,0x04,0x0B,0xFF,0xFF,0x01,0x00,0x0A, /* 00000308 "........" */ + 0x25,0x12,0x0A,0x04,0x0B,0xFF,0xFF,0x0A, /* 00000310 "%......." */ + 0x02,0x00,0x0A,0x26,0x12,0x0A,0x04,0x0B, /* 00000318 "...&...." */ + 0xFF,0xFF,0x0A,0x03,0x00,0x0A,0x27,0x5B, /* 00000320 "......'[" */ + 0x82,0x4F,0x04,0x50,0x45,0x58,0x33,0x08, /* 00000328 ".O.PEX3." */ + 0x5F,0x41,0x44,0x52,0x0C,0x03,0x00,0x03, /* 00000330 "_ADR...." */ + 0x00,0x08,0x5F,0x55,0x49,0x44,0x00,0x08, /* 00000338 ".._UID.." */ + 0x5F,0x42,0x42,0x4E,0x0A,0x06,0x08,0x5F, /* 00000340 "_BBN..._" */ + 0x50,0x52,0x54,0x12,0x2C,0x04,0x12,0x09, /* 00000348 "PRT.,..." */ + 0x04,0x0B,0xFF,0xFF,0x00,0x00,0x0A,0x28, /* 00000350 ".......(" */ + 0x12,0x09,0x04,0x0B,0xFF,0xFF,0x01,0x00, /* 00000358 "........" */ + 0x0A,0x29,0x12,0x0A,0x04,0x0B,0xFF,0xFF, /* 00000360 ".)......" */ + 0x0A,0x02,0x00,0x0A,0x2A,0x12,0x0A,0x04, /* 00000368 "....*..." */ + 0x0B,0xFF,0xFF,0x0A,0x03,0x00,0x0A,0x2B, /* 00000370 ".......+" */ + 0x5B,0x82,0x44,0x0D,0x49,0x53,0x41,0x5F, /* 00000378 "[.D.ISA_" */ + 0x08,0x5F,0x41,0x44,0x52,0x0C,0x00,0x00, /* 00000380 "._ADR..." */ + 0x11,0x00,0x5B,0x82,0x44,0x04,0x4B,0x42, /* 00000388 "..[.D.KB" */ + 0x44,0x5F,0x08,0x5F,0x48,0x49,0x44,0x0C, /* 00000390 "D_._HID." */ + 0x41,0xD0,0x03,0x03,0x14,0x09,0x5F,0x53, /* 00000398 "A....._S" */ + 0x54,0x41,0x00,0xA4,0x0A,0x0F,0x14,0x29, /* 000003A0 "TA.....)" */ + 0x5F,0x43,0x52,0x53,0x00,0x08,0x54,0x4D, /* 000003A8 "_CRS..TM" */ + 0x50,0x5F,0x11,0x18,0x0A,0x15,0x47,0x01, /* 000003B0 "P_....G." */ + 0x60,0x00,0x60,0x00,0x01,0x01,0x47,0x01, /* 000003B8 "`.`...G." */ + 0x64,0x00,0x64,0x00,0x01,0x01,0x22,0x02, /* 000003C0 "d.d..."." */ + 0x00,0x79,0x00,0xA4,0x54,0x4D,0x50,0x5F, /* 000003C8 ".y..TMP_" */ + 0x5B,0x82,0x33,0x4D,0x4F,0x55,0x5F,0x08, /* 000003D0 "[.3MOU_." */ + 0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x0F, /* 000003D8 "_HID.A.." */ + 0x13,0x14,0x09,0x5F,0x53,0x54,0x41,0x00, /* 000003E0 "..._STA." */ + 0xA4,0x0A,0x0F,0x14,0x19,0x5F,0x43,0x52, /* 000003E8 "....._CR" */ + 0x53,0x00,0x08,0x54,0x4D,0x50,0x5F,0x11, /* 000003F0 "S..TMP_." */ + 0x08,0x0A,0x05,0x22,0x00,0x10,0x79,0x00, /* 000003F8 "..."..y." */ + 0xA4,0x54,0x4D,0x50,0x5F,0x5B,0x82,0x47, /* 00000400 ".TMP_[.G" */ + 0x04,0x46,0x44,0x43,0x30,0x08,0x5F,0x48, /* 00000408 ".FDC0._H" */ + 0x49,0x44,0x0C,0x41,0xD0,0x07,0x00,0x14, /* 00000410 "ID.A...." */ + 0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A, /* 00000418 "._STA..." */ + 0x0F,0x14,0x2C,0x5F,0x43,0x52,0x53,0x00, /* 00000420 "..,_CRS." */ + 0x08,0x42,0x55,0x46,0x30,0x11,0x1B,0x0A, /* 00000428 ".BUF0..." */ + 0x18,0x47,0x01,0xF2,0x03,0xF2,0x03,0x00, /* 00000430 ".G......" */ + 0x04,0x47,0x01,0xF7,0x03,0xF7,0x03,0x00, /* 00000438 ".G......" */ + 0x01,0x22,0x40,0x00,0x2A,0x04,0x00,0x79, /* 00000440 "."@.*..y" */ + 0x00,0xA4,0x42,0x55,0x46,0x30, +}; Index: src/mainboard/asus/a8v/acpi-dsdt.aml =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Property changes on: src/mainboard/asus/a8v/acpi-dsdt.aml ___________________________________________________________________ Name: svn:mime-type + application/octet-stream Index: src/mainboard/asus/a8v/Options.lb =================================================================== --- src/mainboard/asus/a8v/Options.lb (revision 0) +++ src/mainboard/asus/a8v/Options.lb (revision 0) @@ -0,0 +1,320 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2006 AMD +## Written by Yinghai Lu for AMD. +## +## Copyright (C) 2006 MSI +## Written by Bingxun Shi for MSI. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses IRQ_SLOT_COUNT +##uses HAVE_OPTION_TABLE +uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS +uses CONFIG_IOAPIC +uses CONFIG_SMP +uses FALLBACK_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses STACK_SIZE +uses HEAP_SIZE +##uses USE_OPTION_TABLE +##uses CONFIG_LB_MEM_TOPK + +uses HAVE_ACPI_TABLES + +uses LB_CKS_RANGE_START +uses LB_CKS_RANGE_END +uses LB_CKS_LOC +uses MAINBOARD +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_VENDOR +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses LINUXBIOS_EXTRA_VERSION +uses _RAMBASE +uses CONFIG_GDB_STUB +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +#bx_b001- uses K8_HW_MEM_HOLE_SIZEK +uses K8_HT_FREQ_1G_SUPPORT + +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE +uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_USE_INIT + +uses ENABLE_APIC_EXT_ID +uses APIC_ID_OFFSET +uses LIFT_BSP_APIC_ID + +uses HT_CHAIN_UNITID_BASE +uses HT_CHAIN_END_UNITID_BASE +#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 +uses SB_HT_CHAIN_UNITID_OFFSET_ONLY +#bx_b005+ +uses SB_HT_CHAIN_ON_BUS0 + +## ROM_SIZE is the size of boot ROM that this board will use. +#512K bytes +default ROM_SIZE=524288 + +#1M bytes +#bx- default ROM_SIZE=1048576 + +## +## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use +## +#default FALLBACK_SIZE=131072 +#256K +default FALLBACK_SIZE=0x40000 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=11 + +## +## Build code to export an x86 MP table +## Useful for specifying IRQ routing values +## +default HAVE_MP_TABLE=1 + +## +## Build code to export a CMOS option table +## +##default HAVE_OPTION_TABLE=1 + +## +## Move the default LinuxBIOS cmos range off of AMD RTC registers +## +default LB_CKS_RANGE_START=49 +default LB_CKS_RANGE_END=122 +default LB_CKS_LOC=123 + +## +## Build code for SMP support +## Only worry about 2 micro processors +## +default CONFIG_SMP=1 +default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_PHYSICAL_CPUS=1 +default CONFIG_LOGICAL_CPUS=1 + +#acpi +default HAVE_ACPI_TABLES=1 + +#CHIP_NAME ? +#default CONFIG_CHIP_NAME=1 + +#1G memory hole +#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000 + +#Opteron K8 1G HT Support +default K8_HT_FREQ_1G_SUPPORT=1 + +##HT Unit ID offset, default is 1, the typical one +default HT_CHAIN_UNITID_BASE=0x0 + +##real SB Unit ID, default is 0x20, mean dont touch it at last +#default HT_CHAIN_END_UNITID_BASE=0x0 + +#make the SB HT chain on bus 0, default is not (0) +#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2 + +##bx_b005+ make the SB HT chain on bus 0 +default SB_HT_CHAIN_ON_BUS0=1 + +##only offset for SB chain?, default is yes(1) +default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 + +#VGA +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcc000 +default DCACHE_RAM_SIZE=0x4000 +default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 +default CONFIG_USE_INIT=0 + +default ENABLE_APIC_EXT_ID=1 +default APIC_ID_OFFSET=0x10 +default LIFT_BSP_APIC_ID=0 + + +## +## Build code to setup a generic IOAPIC +## +default CONFIG_IOAPIC=1 + +## +## Clean up the motherboard id strings +## +default MAINBOARD_PART_NUMBER="a8v" +default MAINBOARD_VENDOR="ASUS" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 256K heap +## +default HEAP_SIZE=0x40000 + +#more 1M for pgtbl +##default CONFIG_LB_MEM_TOPK=2048 + + +## +## Only use the option table in a normal image +## +##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE + +## +## LinuxBIOS C code runs at this location in RAM +## +default _RAMBASE=0x00004000 + +## +## Load the payload from the ROM +## +default CONFIG_ROM_PAYLOAD = 1 + +### +### Defaults of options that you may want to override in the target config file +### + +## +## The default compiler +## +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## +## Select power on after power fail setting +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" + +### End Options.lb +end Index: src/mainboard/asus/a8v/acpi_tables.c =================================================================== --- src/mainboard/asus/a8v/acpi_tables.c (revision 0) +++ src/mainboard/asus/a8v/acpi_tables.c (revision 0) @@ -0,0 +1,145 @@ +/* + * LinuxBIOS ACPI Table support + * written by Stefan Reinauer + * ACPI FADT, FACS, and DSDT table support added by + * Nick Barker , and those portions + * (C) Copyright 2004 Nick Barker + * (C) Copyright 2005 Stefan Reinauer + */ + +#include +#include +#include +#include +#include +#include + + +extern unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x5238, 0); + if (dev) { + res = find_resource(dev, 0x61); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, res->base, 0x0, 0x0, 0xff); + } + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base=0x18; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 0x2, + 0xfec00000UL, 0); + + /* Write NB IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 0x3, + 0xfecc0000UL, gsi_base); + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); //IRQ9 ACPI active low + + current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); //IRQ0 -> APIC IRQ2 + + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_mcfg_t *mcfg; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16byte */ + start = ( start + 0x0f ) & -0x10; + current = start; + + printk_info("ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + printk_debug("ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *)current; + current += ((acpi_header_t *)AmlCode)->length; + memcpy((void *)dsdt,(void *)AmlCode, ((acpi_header_t *)AmlCode)->length); + dsdt->checksum = 0; // don't trust intel iasl compiler to get this right + dsdt->checksum = acpi_checksum(dsdt,dsdt->length); + printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length); + printk_debug("ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt,facs,dsdt); + acpi_add_table(rsdt,fadt); + + printk_debug("ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdt,hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk_debug("ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current+=madt->header.length; + acpi_add_table(rsdt,madt); + + + printk_debug("ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current+=mcfg->header.length; + acpi_add_table(rsdt, mcfg); + + /* SRAT */ + printk_debug("ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current+=srat->header.length; + acpi_add_table(rsdt,srat); + + printk_info("ACPI: done.\n"); + return current; +} + Index: src/mainboard/asus/a8v/failover.c =================================================================== --- src/mainboard/asus/a8v/failover.c (revision 0) +++ src/mainboard/asus/a8v/failover.c (revision 0) @@ -0,0 +1,70 @@ +#define ASSEMBLY 1 +#include +#include +#include +#include +#include +#include +#include "pc80/mc146818rtc_early.c" +//#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "northbridge/amd/amdk8/reset_test.c" + +#if CONFIG_LOGICAL_CPUS==1 +#include "cpu/amd/dualcore/dualcore_id.c" +#endif + + +static unsigned long main(unsigned long bist) +{ + /* Make cerain my local apic is useable */ + enable_lapic(); + + /* Is this a cpu only reset? */ + if (early_mtrr_init_detected()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + /* Is this a secondary cpu? */ + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* Setup the 8111 */ +// amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && 1) { +//last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} Index: src/mainboard/asus/a8v/mb_sysconf.h =================================================================== --- src/mainboard/asus/a8v/mb_sysconf.h (revision 0) +++ src/mainboard/asus/a8v/mb_sysconf.h (revision 0) @@ -0,0 +1,38 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { +// unsigned char bus_isa; + // unsigned char bus_mcp55[8]; //1 + // unsigned apicid_mcp55; + // unsigned bus_type[256]; + +}; + +#endif + Index: src/mainboard/asus/a8v/cache_as_ram_auto.c =================================================================== --- src/mainboard/asus/a8v/cache_as_ram_auto.c (revision 0) +++ src/mainboard/asus/a8v/cache_as_ram_auto.c (revision 0) @@ -0,0 +1,444 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 AMD + * Written by Yinghai Lu for AMD. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __ROMCC__ + +//#define K8_ALLOCATE_IO_RANGE 1 + +#define RAMINIT_SYSINFO 1 + +#define CACHE_AS_RAM_ADDRESS_DEBUG 0 + + unsigned int get_sbdn(unsigned bus); + + +//used by raminit +#define QRANK_DIMM_SUPPORT 1 + +//used by init_cpus and fidvid +#define K8_SET_FIDVID 1 +//if we want to wait for core1 done before DQS training, set it to 0 +#define K8_SET_FIDVID_CORE0_ONLY 1 + +#define DEBUG_SMBUS 1 + +#include +#include +#include +#include +#include +#include +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" + +#include +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 + #include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "northbridge/amd/amdk8/early_ht.c" + + +#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) +#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) + +#include + + +//#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +static void memreset_setup(void) +{ +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define K8_4RANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "sdram/generic_sdram.c" + + /* msi does not want the default */ +//#include "resourcemap.c" +#include "cpu/amd/dualcore/dualcore.c" + +//#define MCP55_NUM 1 +//#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" +//set GPIO to input mode +//#define MCP55_MB_SETUP \ + // RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ + // RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + // RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + // RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ + +//#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" + +#include "northbridge/amd/amdk8/resourcemap.c" + + +void activate_spd_rom(const struct mem_controller *ctrl) +{ + +} + + +void hard_reset(void) +{ + /* nothing to do */ + print_info("NO HARD RESET FIX ME!\n"); +} + + + + + +void soft_reset(void) +{ + uint8_t tmp; + set_bios_reset(); + print_info("soft reset \r\n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); +// mdelay(10); + /* PCI reset done */ + tmp &=~1; + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + +// outb(0x02, 0x0cf9); +// outb(0x06, 0x0cf9); /* this value will assert RESET_L and LDTRST_L */ + + print_info("soft reset done\r\n"); +} + + unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_VIA, 0x3227), + bus); + + return (dev>>15) & 0x1f; + +} + + +#if USE_FALLBACK_IMAGE == 1 + +//#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" +//#include "northbridge/amd/amdk8/early_ht.c" + + +static void sio_setup(void) +{ + + unsigned value; + uint32_t dword; + uint8_t byte; + +// byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + // byte |= 0x20; +// pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + + // dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + // dword |= (1<<0); + // pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + + +} + + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ +// unsigned last_boot_normal_x = last_boot_normal(); +//FIXME + + unsigned last_boot_normal_x = 1; +// print_info("failover process\r\n"); + + u8 reg; + + pnp_enter_ext_func_mode(SERIAL_DEV); + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* we have 24MHz input */ + + reg = pnp_read_config(SERIAL_DEV, 0x2A); + pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1)); /* we have GPIO for KB/MS PIN */ + + reg = pnp_read_config(SERIAL_DEV, 0x2C); + pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0)); /* we have all RESTOUT and even some reserved bits too */ + + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input + pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val + pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion + pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input + pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val + pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion + pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5 + pnp_exit_ext_func_mode(GPIO_DEV); + + + w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + print_info("now booting... fallback\r\n"); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + sio_setup(); + + // /* Setup the mcp55 */ +// vt8237_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + //print_info("JMP normal image\r\n"); + + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b"(cpu_init_detectedx) /* inputs */ + ); + + fallback_image: + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); + +} + + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + + static const uint16_t spd_addr [] = { + (0xa<<3)|0, (0xa<<3)|2, 0, 0, + (0xa<<3)|1, (0xa<<3)|3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + (0xa<<3)|4, (0xa<<3)|6, 0, 0, + (0xa<<3)|5, (0xa<<3)|7, 0, 0, +#endif +}; + unsigned bsp_apicid = 0; + int needs_reset; + struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + char *p ; + u8 reg; + + +//move CPU INIT back here + + + + pnp_enter_ext_func_mode(SERIAL_DEV); + reg = pnp_read_config(SERIAL_DEV, 0x24); + pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* we have 24MHz input */ + + reg = pnp_read_config(SERIAL_DEV, 0x2A); + pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1)); /* we have GPIO for KB/MS PIN */ + + reg = pnp_read_config(SERIAL_DEV, 0x2C); + pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0)); /* we have all RESTOUT and even some reserved bits too */ + + pnp_exit_ext_func_mode(SERIAL_DEV); + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input + pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val + pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion + pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input + pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val + //0x10 seems to control something with SGD VIA + + pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion + pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5 + pnp_exit_ext_func_mode(GPIO_DEV); + + + w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + print_info("now booting... real_main\r\n"); + + if (bist == 0) { + //init_cpus(cpu_init_detectedx); + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + // enable_lapic(); + init_timer(); + + print_info("now booting... after init_cpus\r\n"); + + mdelay(1000); + print_info("now booting... after udelay\r\n"); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + +/* + { + + int i; + unsigned long tmp; + for (i=0;i<32;i++) { + tmp = pci_read_config16(PCI_DEV(0, 0x18, 1), 0x60); + print_debug_hex16(i); + print_debug_hex16(tmp); + tmp = pci_read_config16(PCI_DEV(0, 0x18, 1), 0x0); + print_debug_hex16(i); + print_debug_hex16(tmp); + + } + } +*/ + print_info("now booting... bist\r\n"); + + // setup_a8v_resource_map(); + setup_default_resource_map(); + + print_info("now booting... resource map\r\n"); + + setup_coherent_ht_domain(); + + print_info("now booting... HT domain\r\n"); + + + wait_all_core0_started(); + + print_info("now booting... Core0 started\r\n"); + +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); + //wait_all_other_cores_started(bsp_apicid); +#endif + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + + print_info("now booting... htchains x\r\n"); + + + needs_reset = optimize_link_coherent_ht(); + + needs_reset |= optimize_link_incoherent_ht(sysinfo); + +// needs_reset |= mcp55_early_setup_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + //It's the time to set ctrl now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + + memreset_setup(); + + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + post_cache_as_ram(); + +} Index: src/mainboard/asus/a8v/fadt.c =================================================================== --- src/mainboard/asus/a8v/fadt.c (revision 0) +++ src/mainboard/asus/a8v/fadt.c (revision 0) @@ -0,0 +1,155 @@ +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + * (C) Copyright 2004 Nick Barker + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include +#include + +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ + acpi_header_t *header=&(fadt->header); + + memset((void *)fadt,0,sizeof(acpi_fadt_t)); + memcpy(header->signature,"FACP",4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id,"LXBIOS",6); + memcpy(header->oem_table_id,"LXBACPI ",8); + memcpy(header->asl_compiler_id,"LXB",8); + header->asl_compiler_revision=0; + + fadt->firmware_ctrl=facs; + fadt->dsdt= dsdt; + fadt->preferred_pm_profile=0; + fadt->sci_int=9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = 0x500; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = 0x504; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = 0x508; + fadt->gpe0_blk = 0x520; + fadt->gpe1_blk = 0x0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 90; //90; + fadt->p_lvl3_lat = 900; //900; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; + fadt->duty_width = 1; //?? + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x1; //fixme 5-10 + fadt->flags = 0x4a5; //FIXME 5-9 + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 4; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = 0x500; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 2; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = 0x504; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = 0x0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 4; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = 0x508; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0x520; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} Index: src/mainboard/asus/a8v/Config.lb =================================================================== --- src/mainboard/asus/a8v/Config.lb (revision 0) +++ src/mainboard/asus/a8v/Config.lb (revision 0) @@ -0,0 +1,325 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2006 AMD +## Written by Yinghai Lu for AMD. +## +## Copyright (C) 2006 MSI +## Written by Bingxun Shi for MSI. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_ROM_PAYLOAD = 1 + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +arch i386 end + + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#dir /drivers/ati/ragexl +#needed by irq_tables and mptable and acpi_tables + +if HAVE_ACPI_TABLES + object fadt.o + object dsdt.o + object acpi_tables.o +end + + +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + + +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds + mainboardinit southbridge/via/vt8237r/romstrap.inc + ldscript /southbridge/via/vt8237r/romstrap.lds + +end + +mainboardinit cpu/x86/32bit/entry32.inc + +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +if USE_DCACHE_RAM +else +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc +end + +## +## Include an id string (For safe flashing) +## +##mainboardinit southbridge/nvidia/mcp55/id.inc +##ldscript /southbridge/via/vt8237/id.lds + +## +## ROMSTRAP table for MCP55 +## +##if USE_FALLBACK_IMAGE +## mainboardinit southbridge/nvidia/mcp55/romstrap.inc +## ldscript /southbridge/nvidia/mcp55/romstrap.lds +##end + +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else +# ROMCC +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit cpu/x86/sse/enable_sse.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/sse/disable_sse.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +end + +## +## Include the secondary Configuration files +## +if CONFIG_CHIP_NAME + config chip.h +end + +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_939 + device apic 0 on end + end + end + + device pci_domain 0 on + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r + register "enable_native_ide" = "0" + device pci 0.0 on end # HT + device pci 11.0 on # LPC + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + + chip superio/winbond/w83627ehg + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off #keyb OFF + end + device pnp 2e.6 off # SERIAL_FALSH + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + # io 0x60 = 0x220 + # io 0x62 = 0x300 + # irq 0x70 = a + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 0x30 0x9 + #GPIO 5 and 2 active + #0xe0 = de + #0xe1 = 01 + #0xe2 = 00 + #0xe3 = 03 + #0xe4 = a4 + #0xe5 = 00 + + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end #end SIO + end #end 11 + + device pci 12.0 off end # VIA LAN + end + + chip southbridge/via/k8t890 + end + + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #mc0 + + end # pci_domain + +end # root_complex Index: src/mainboard/asus/a8v/mptable.c =================================================================== --- src/mainboard/asus/a8v/mptable.c (revision 0) +++ src/mainboard/asus/a8v/mptable.c (revision 0) @@ -0,0 +1,160 @@ +/* generatred by MPTable, version 2.0.15*/ +/* as modified by RGM for LinuxBIOS */ +#include +#include +#include + +void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "A8V-E SE "; + struct mp_config_table *mc; + unsigned int conforms = 0; + int bus_isa = 42; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + +/*Bus: Bus ID Type*/ + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); + smp_write_bus(mc, 4, "PCI "); + smp_write_bus(mc, 5, "PCI "); + smp_write_bus(mc, 6, "PCI "); + smp_write_bus(mc, bus_isa, "ISA "); +/*I/O APICs: APIC ID Version State Address*/ + + smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + + //fixme - this should be read out from NB + smp_write_ioapic(mc, 3, 0x20, 0xfecc0000); +/*I/O Ints: Type Polarity Trigger Bus ID/IRQ APIC ID/PIN# +INTA# => IRQ16 +INTB# => IRQ17 +INTC# => IRQ18 +INTD# => IRQ19 T o + A C +IDE (Native Mode)/SATA IRQ & INTE => IRQ20 0:0f.0 pinB 0:0f.1 pinA + I +USB IRQ (all 5 functions) and INTF => IRQ21 0:10.0-4 0 1 A 2 3 B 4 C +AC'97 / MC'97 IRQ and INTG => IRQ22 0:11.5 C 0:11.6 +LAN IRQ and INTH => IRQ23 - have not + + +*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x2, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, 0x2, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, 0x2, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, 0x2, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, 0x2, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, 0x2, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, 0x2, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, 0x2, 0x13); //IRQ19 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, 0x2, 0x11); //IRQ17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, 0x2, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, 0x2, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, 0x2, 0x10); //IRQ16 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, 0x2, 0x12); //IRQ18 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, 0x2, 0x13); //IRQ19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, 0x2, 0x10); //IRQ16 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, 0x2, 0x11); //IRQ17 + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, 0x2, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, 0x2, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, 0x2, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, 0x2, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, 0x2, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, 0x2, 0x16); + + //? + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, 0x3, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, 0x3, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, 0x3, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, 0x3, 0x3); + + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, 0x3, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, 0x3, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, 0x3, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, 0x3, 0x13); + + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, 0x3, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, 0x3, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, 0x3, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, 0x3, 0x3); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, 0x3, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, 0x3, 0x5); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, 0x3, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, 0x3, 0x7); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, 0x3, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, 0x3, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, 0x3, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, 0x3, 0xb); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, 0x3, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, 0x3, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, 0x3, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, 0x3, 0xf); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, 0x3, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, 0x3, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, 0x3, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, 0x3, 0x13); + +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + //printf_debug("Wrote the mp table end at: %p - %p\n", + // mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Index: src/mainboard/asus/a8v/irq_tables.c =================================================================== --- src/mainboard/asus/a8v/irq_tables.c (revision 0) +++ src/mainboard/asus/a8v/irq_tables.c (revision 0) @@ -0,0 +1,56 @@ +/* This file was generated by getpir.c, do not modify! + * (but if you do, please run checkpir on it to verify) + * + * Contains the IRQ Routing Table dumped directly from your + * memory, which BIOS sets up. + * + * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx + */ + +#ifdef GETPIR +#include "pirq_routing.h" +#else +#include +#endif + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*18, /* There can be total 18 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0x820, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x596, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xe3, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0b<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x08<<3)|0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x03, 0xdeb8}, {0x03, 0xdeb8}, {0x03, 0xdeb8}, {0x03, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x07<<3)|0x0, {{0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0xdeb8}, {0x02, 0x0deb8}}, 0x0, 0x0}, + {0x02,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x4, 0x0}, + {0x03,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x5, 0x0}, + {0x04,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x6, 0x0}, + {0x05,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0}, + {0x06,(0x00<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x7, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x02<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x03<<3)|0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x03<<3)|0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x03<<3)|0x2, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x03<<3)|0x3, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0x0deb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ +return copy_pirq_routing_table(addr); +} Index: src/mainboard/asus/a8v/chip.h =================================================================== --- src/mainboard/asus/a8v/chip.h (revision 0) +++ src/mainboard/asus/a8v/chip.h (revision 0) @@ -0,0 +1,28 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_via_a8v_ops; + +struct mainboard_asus_a8v_config { + int fixup_scsi; + int fixup_vga; + +}; Index: src/mainboard/asus/a8v/dsdt.asl =================================================================== --- src/mainboard/asus/a8v/dsdt.asl (revision 0) +++ src/mainboard/asus/a8v/dsdt.asl (revision 0) @@ -0,0 +1,226 @@ +/* + * Minimalist ACPI DSDT table for EPIA-M / MII + * (C) Copyright 2004 Nick Barker + * (C) Rudolf Marek + * + * ISA portions taken from QEMU acpi-dsdt.dsl + * GPLv2 + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) +{ + /* + * Define the main processor + */ + Scope (\_PR) + { + Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {} + Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * any others would involve declaring the wake up methods + */ + Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + //aaa + Name (_PRT, Package () { + Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, //slot 0xB + Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, //Slot 0xC + Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, //Slot 0xD + Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 }, + Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, //0xf SATA IRQ 20 + Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, //0xf NAtive IDE IRQ 20 + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, //USB routing + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 }, + Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, //AC97 MC97 + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, //PCIE16 bridge IRQ27 + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, //PCIE bridge IRQ31 + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, //IRQ36 + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, //IRQ39 + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } //IRQ43 + }) + + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (_UID, 0x00) + Name (_BBN, 0x02) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, //PCIE IRQ24-IRQ27 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + } //end of PCIEG + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (_UID, 0x00) + Name (_BBN, 0x03) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, //PCIE IRQ28-IRQ31 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + } //end of PEX0 + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (_UID, 0x00) + Name (_BBN, 0x04) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, //PCIE IRQ32-IRQ35 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + } //end f PEX1 + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (_UID, 0x00) + Name (_BBN, 0x05) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, //PCIE IRQ36-IRQ39 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + } //end f PEX2 + + Device (PEX3) + { + Name (_ADR, 0x00030003) + Name (_UID, 0x00) + Name (_BBN, 0x06) + + Name (_PRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, //PCIE IRQ40-IRQ43 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B }, + }) + } //end f PEX3 + + Device (ISA) { + Name (_ADR, 0x00110000) + + /* Keyboard seems to be important for WinXP install */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Address Range Minimum + 0x0060, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IO (Decode16, + 0x0064, // Address Range Minimum + 0x0064, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IRQNoFlags () + {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } //FD END + + } //ISA END + + } // End of PCI0 + + + } // End of _SB + +} // End of Definition Block + Index: src/mainboard/asus/a8v/cmos.layout =================================================================== --- src/mainboard/asus/a8v/cmos.layout (revision 0) +++ src/mainboard/asus/a8v/cmos.layout (revision 0) @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Index: src/mainboard/asus/a8v/mainboard.c =================================================================== --- src/mainboard/asus/a8v/mainboard.c (revision 0) +++ src/mainboard/asus/a8v/mainboard.c (revision 0) @@ -0,0 +1,33 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 MSI + * Written by Bingxun Shi for MSI. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "chip.h" + +#if CONFIG_CHIP_NAME == 1 +struct chip_operations mainboard_asus_a8v_ops = { + CHIP_NAME("A8V Mainboard") +}; +#endif Index: src/lib/malloc.c =================================================================== --- src/lib/malloc.c (revision 2776) +++ src/lib/malloc.c (working copy) @@ -1,10 +1,10 @@ #include #include -#if 0 +#if 1 #define MALLOCDBG(x) #else -#define MALLOCDBG(x) printk_spew x +#define MALLOCDBG(x) printk_debug x #endif extern unsigned char _heap, _eheap; static size_t free_mem_ptr = (size_t)&_heap; /* Start of heap */